View CY7C09389V-9AC_4250783.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

3.3v 16k/32k/64k x 16/18 synchronous dual-port static ram cy7c09269v/79v/89v cy7c09369v/79v/89v cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06056 rev. *c revised march 25, 2009 features true dual-ported memory cells that allow simultaneous access of the same memory location six flow through/pipelined devices: ? 16k x 16/18 organization (cy7c09269v/369v) ? 32k x 16/18 organization (cy7c09279v/379v) ? 64k x 16/18 organization (cy7c09289v/389v) three modes: ? flow through ? pipelined ? burst pipelined output mode on both ports allows fast 100 mhz operation 0.35 micron cmos for optimum speed and power high speed clock to data access: 6.5 [1, 2] , 7.5 [2] , 9, 12 ns (max) 3.3v low operating power: ? active = 115 ma (typical) ? standby = 10 a (typical) fully synchronous interface for easier operation burst counters increment addresses internally: ? shorten cycle times ? minimize bus noise ? supported in flow through and pipelined modes dual chip enables easy depth expansion upper and lower byte controls for bus matching automatic power down commercial and industrial temperature ranges pb-free 100-pin tqfp package available logic block diagram r/ w l 1 0 0/1 ce 0l ce 1l lb l oe l ub l 1b 0/1 0b 1a 0a ba ft /pipe l i/o 8/9l ?i/o 15/17l i/o 0l ?i/o 7/8l i/o control counter/ address register decode a 0l ?a 13/14/15l clk l ads l cnten l cntrst l true dual-ported ram array r/ w r 1 0 0/1 ce 0r ce 1r lb r oe r ub r 1b 0/1 0b 1a 0a b a ft /pipe r i/o control counter/ address register decode 14/15/16 8/9 8/9 i/o 8/9r ?i/o 15/17r i/o 0r ?i/o 7/8r a 0r ?a 13/14/15r clk r ads r cnten r cntrst r 14/15/16 8/9 8/9 [3] [4] [3] [4] [5] [5] notes 1. call for availability. 2. see page 6 for load conditions. 3. i/o 8 ?i/o 15 for x16 devices; i/o 9 ?i/o 17 for x18 devices. 4. i/o 0 ?i/o 7 for x16 devices. i/o 0 ?i/o 8 for x18 devices. 5. a 0 ?a 13 for 16k; a 0 ?a 14 for 32k; a 0 ?a 15 for 64k devices. [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 2 of 19 pinouts figure 1. 100-pin tqfp (top view) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 a9r a10r a11r a12r a13r a14r ubr nc lbr ce1r cntrstr oer ft /piper nc a15r gnd r/wr gnd i/o15r i/o14r i/o13r i/o12r i/o11r i/o10r ce0r 58 57 56 55 54 53 52 51 cy7c09279v (32k x 16) cy7c09269v (16k x 16) a9l a10l a11l a12l a13l a14l ubl nc lbl ce1l cntrstl oel ft /pipel nc a15l vcc r/wl gnd i/o15l i/o14l i/o13l i/o12l i/o11l i/o10l ce0l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 a8l a7l a6l a5l a4l a3l clkl a1l cntenl gnd adsr a0r a1r a0l a2l clkr cntenr a2r a3r a4r a5r a6r a7r a8r adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc i/o9r i/o8r i/o7r vcc i/o6r i/01r i/o4r i/o2r gnd i/o0l i/o2l i/o3l i/o3r i/o5r i/o1l gnd i/o4l i/o5l i/o6l i/o7l vcc i/o8l i/o9l i/o0r 33 32 31 30 29 28 27 26 cy7c09289v (64k x 16) [6] [7] [8] [8] [6] [7] notes 6. this pin is nc for cy7c09269v. 7. this pin is nc for cy7c09269v and cy7c09279v. 8. for cy7c09269v and cy7c09279v, pin #18 connected to v cc is pin compatible to an idt 5v x16 pipelined device; connecting pin #18 and #58 to gnd is pin compatible to an idt 5v x16 flow through device. [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 3 of 19 figure 2. 100-pin tqfp (top view) selection guide specifications cy7c09269v/79v/89v cy7c09369v/79v/89v -6 [1, 2] cy7c09269v/79v/89v cy7c09369v/79v/89v -7 [2] cy7c09269v/79v/89v cy7c09369v/79v/89v -9 cy7c09269v/79v/89v cy7c09369v/79v/89v -12 f max2 (mhz) (pipelined) 100 83 67 50 max. access time (ns) (clock to data, pipelined) 6.5 7.5 9 12 typical operating current i cc (ma) 175 155 135 115 typical standby current for i sb1 (ma) (both ports ttl level) 25 25 20 20 typical standby current for i sb3 ( a) (both ports cmos level) 10 10 10 10 pinouts (continued) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 a8r a9r a10r a11r a12r a13r ce0r a15r ubr cntrstr r/wr ft /piper i/o17r lbr a14r gnd oer gnd i/o16r i/o15r i/o14r i/o13r i/o12r i/o11r ce1r 58 57 56 55 54 53 52 51 cy7c09379v (32k x 18) cy7c09369v (16k x 18) a9l a10l a11l a12l a13l a14l ce1l lbl ce0l r/wl oel i/o17l i/o16l ubl a15l vcc ft /pipel gnd i/o15l i/o14l i/o13l 1/012l i/o11l i/o10l cntrstl 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 a8l a7l a6l a5l a4l a3l clkl a1l cntenl gnd gnd cntenr a0r a0l a2l adsr clkr a1r a2r a3r a4r a5r a6r a7r adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 i/10r i/o9r i/o8r i/o7r vcc i/o6r i/01r i/o4r i/o2r gnd i/o0l i/o2l i/o3l i/o3r i/o5r i/o1l gnd i/o4l i/o5l i/o6l i/o7l vcc i/o8l i/o9l i/o0r 33 32 31 30 29 28 27 26 cy7c09389v (64k x 18) [9] [10] [9] [10] notes 9. this pin is nc for cy7c09369v. 10. this pin is nc for cy7c09369v and cy7c09379v. [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 4 of 19 functional description the cy7c09269v/79v/89v and cy7c09369v/79v/89v are high speed 3.3v synchronous cmos 16k, 32k, and 64k x 16/18 dual-port static rams. two por ts are provided, permitting independent, simultaneous access for reads and writes to any location in memory [11] . registers on control, address, and data lines allow for minimal setup and hold times. in pipelined output mode, data is registered for decreased cycle time. clock to data valid t cd2 = 6.5 ns [1, 2] (pipelined). flow through mode can also be used to bypass the pipelined output register to eliminate access latency. in flow through mode, data is available t cd1 = 18 ns after the address is clocked into the device. pipelined output or flow through mode is selected through the ft /pipe pin. each port contains a burst counter on the input address register. the internal write pulse width is independent of the low to high transition of the clock signal. the internal write pulse is self timed to allow the shortest possible cycle times. a high on ce 0 or low on ce 1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. the use of multiple chip enables e nables easier banking of multiple chips for depth expansion configurations. in the pipelined mode, one cycle is required with ce 0 low and ce 1 high to reactivate the outputs. counter enable inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast interleaved memory applications. a port?s burst counter is loaded with the port?s address strobe (ads ). when the port?s count enable (cnten ) is asserted, the address counter increments on ea ch low to high transition of that port?s clock signal. this re ads/writes one word from or into each successive addre ss location, until cnten is deasserted. the counter can address the entire memory array and loop back to the start. counter reset (cntrst ) is used to reset the burst counter. all parts are available in 100-pin thin quad plastic flatpack (tqfp) packages. pin definitions left port right port description a 0l ?a 15l a 0r ?a 15r address inputs (a 0 ?a 14 for 32k, a 0 ?a 13 for 16k devices). ads l ads r address strobe input. used as an address qualifier. this signal must be asserted low to access the part using an externally suppl ied address. asserting this signal low also loads the burst counter with the address present on the address pins. ce 0l , ce 1l ce 0r ,ce 1r chip enable input. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 v il and ce 1 v ih ). clk l clk r clock signal. this input can be free running or strobed. maximum clock input rate is f max . cnten l cnten r counter enable input. asserting this signal low increments the burst address counter of its respective port on each rising edge of clk. cnten is disabled if ads or cntrst are asserted low. cntrst l cntrst r counter reset input. asserting this signal lo w resets the burst address counter of its respective port to zero. cntrst is not disabled by asserting ads or cnten . i/o 0l ?i/o 17l i/o 0r ?i/o 17r data bus input/output (i/o 0 ?i/o 15 for x16 devices). lb l lb r lower byte select input . asserting this signal low enables read and write operations to the lower byte. (i/o 0 ?i/o 8 for x18, i/o 0 ?i/o 7 for x16) of the memory array. for read operations both the lb and oe signals must be asserted to drive output data on the lower byte of the data pins. ub l ub r upper byte select input. same function as lb , but to the upper byte (i/o 8/9l ?i/o 15/17l ). oe l oe r output enable input. this signal must be asserted low to enable the i/o data pins during read operations. r/w l r/w r read/write enable input . this signal is asserted low to write to the dual port memory array. for read operations, assert this pin high. ft /pipe l ft /pipe r flow through/pipelined select input. for flow through mode operation, assert this pin low. for pipelined mode operation, assert this pin high. gnd ground input . nc no connect . v cc power input . note 11. when writing simultaneously to the same location, the final value cannot be guaranteed. [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 5 of 19 maximum ratings [12] exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..................................... ? 65 c to +150c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage to ground potential .................? 0.5v to +4.6v dc voltage applied to outputs in high z state ..............................................? 0.5v to v cc +0.5v dc input voltage ..........................................? 0.5v to v cc +0.5v output current into outputs (l ow)............................. 20 ma static discharge voltage.......................................... > 1100v (per mil-std-883, method 3015) latch up current.................................................... > 200 ma operating range range ambient temperature v cc commercial 0c to +70c 3.3v 300 mv industrial ?40c to +85c 3.3v 300 mv electrical characteristics over the operating range parameter description cy7c09269v/79v/89v cy7c09369v/79v/89v unit -6 [1, 2] -7 [2] -9 -12 min typ max min typ max min typ max min typ max v oh output high voltage (v cc = min. l oh = ?4.0 ma) 2.4 2.4 2.4 2.4 v v ol output low voltage (v cc = min. l oh = +4.0 ma) 0.4 0.4 0.4 0.4 v v ih input high voltage 2.0 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 0.8 v i oz output leakage current ?10 10 ?10 10 ?10 10 ?10 10 a i cc operating current (v cc = max, i out = 0 ma) outputs disabled com?l. 175 320 155 275 135 230 115 180 ma indust. 275 390 185 300 ma i sb1 standby current (both ports ttl level) [13] ce l & ce r v ih , f = f max com?l. 25 95 25 85 20 75 20 70 ma indust. 85 120 35 85 ma i sb2 standby current (one port ttl level) [13] ce l | ce r v ih , f = f max com?l. 115 175 105 165 95 155 85 140 ma indust. 165 210 105 165 ma i sb3 standby current (both ports cmos level) [13] ce l & ce r v cc ? 0.2v, f = 0 com?l. 10 250 10 250 10 250 10 250 a indust. 10 250 10 250 a i sb4 standby current (one port cmos level) [13] ce l | ce r v ih , f = f max com?l. 105 135 95 125 85 115 75 100 ma indust. 125 170 95 125 ma capacitance tested initially and after any design or proce ss changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 10 pf c out output capacitance 10 pf notes 12. the voltage on any input or i/o pin can not exceed the power pin during power up. 13. ce l and ce r are internal signals. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 v il and ce 1 v ih ). [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 6 of 19 figure 3. ac test loads and waveforms figure 4. ac test loads (applicable to -6 and -7 only) [14] (a) normal load (load 1) r1 = 590 3.3v output r2 = 435 c= 30 pf v th =1.4v output c= 30 pf (b) thvenin equivalent (load 1) (c) three-state delay(load 2) r1 = 590 r2 = 435 3.3v output c= 5pf r th =250 (used for t cklz , t olz , and t ohz including scope and jig) v th =1.4v output c (a) load 1 (-6 and -7 only) r = 50 z 0 = 50 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses 0.00 0.1 0 0.20 0.30 0.40 0.50 0.60 5 3 0 3 5 2 0 2 5 1 0 1 (b) load derating curve capacitance (pf) ' (ns) for all -7 access times note 14. test conditions: c = 10 pf. [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 7 of 19 switching characteristics over the operating range parameter description cy7c09269v/79v/89v cy7c09369v/79v/89v unit -6 [1, 2] -7 [2] -9 -12 min max min max min max min max f max1 f max flow through 53 45 40 33 mhz f max2 f max pipelined 100 83 67 50 mhz t cyc1 clock cycle time - flow through 19 22 25 30 ns t cyc2 clock cycle time - pipelined 10 12 15 20 ns t ch1 clock high time - flow through 6.5 7.5 12 12 ns t cl1 clock low time - flow through 6.5 7.5 12 12 ns t ch2 clock high time - pipelined 4 5 6 8 ns t cl2 clock low time - pipelined 4 5 6 8 ns t r clock rise time 3333ns t f clock fall time 3333ns t sa address set-up time 3.5 4 4 4 ns t ha address hold time 0 0 1 1 ns t sc chip enable setup time 3.5 4 4 4 ns t hc chip enable hold time 0 0 1 1 ns t sw r/w set-up time 3.5 4 4 4 ns t hw r/w hold time 0 0 1 1 ns t sd input data setup time 3.5 4 4 4 ns t hd input data hold time 0 0 1 1 ns t sad ads set-up time 3.5444ns t had ads hold time 0011ns t scn cnten setup time 3.5 4.5 5 5 ns t hcn cnten hold time 0011ns t srst cntrst setup time 3.5444ns t hrst cntrst hold time 0011ns t oe output enable to data valid 8 9 10 12 ns t olz [15,16] oe to low z 2222ns t ohz [15,16] oe to high z 17171717ns t cd1 clock to data valid - flow through 15 18 20 25 ns t cd2 clock to data valid - pipelined 6.5 7.5 9 12 ns t dc data output hold after clock high 2 2 2 2 ns t ckz [15,16] clock high to output high z 2 9 2 9 2 9 2 9 ns t ckz [15,16] clock high to output low z 2 2 2 2 ns port to port delays t cwdd write port clock high to read data delay 30 35 40 40 ns t ccs clock to clock setup time 9 10 15 15 ns notes 15. test conditions used are load 2. 16. this parameter is guaranteed by design, but it is not production tested. [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 8 of 19 switching waveforms figure 5. read cycle for flow through output (ft /pipe = v il ) [17, 18, 19, 20] figure 6. read cycle for pipelined operation (ft /pipe = v ih ) [17, 18, 19, 20] notes 17. oe is asynchronously c ontrolled; all other inputs are synchronous to the rising clock edge. 18. ads = v il , cnten and cntrst = v ih . 19. the output is disabled (high impedance state) by ce 0 =v ih or ce 1 = v il following the next rising edge of the clock. 20. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. t ch1 t cl1 t cyc1 t sc t hc t dc t ohz t oe t sc t hc t sw t hw t sa t ha t cd1 t ckhz t dc t olz t cklz a n a n+1 a n+2 a n+3 q n q n+1 q n+2 clk ce 0 ce 1 r/w address data out oe t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce 0 ce 1 r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 9 of 19 figure 7. bank select pipelined read [21, 22] figure 8. left port write to flow through right port read [23, 24, 25, 26] notes 21. in this depth expansion example, b1 repr esents bank #1 and b2 is bank #2; each ba nk consists of one cypress dual-port device from this datasheet. address (b1) = address (b2) . 22. ub , lb , oe and ads = v il ; ce 1(b1) , ce 1(b2) , r/w , cnten , and cntrst = v ih . 23. the same waveforms apply for a right port write to flow through left port read. 24. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . 25. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 26. it t ccs maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs >maximum specified, then data is not valid until t ccs + t cd1 . t cwdd does not apply in this case. switching waveforms (continued) d 3 d 1 d 0 d 2 a 0 a 1 a 2 a 3 a 4 a 5 d 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk l address (b1) ce 0(b1) data out(b2) data out(b1) address (b2) ce 0(b2) t sa t ha t sw t hw t sd t hd match valid t ccs t sw t hw t dc t cwdd t cd1 match t sa t ha match no match no valid valid t dc t cd1 clk l r/ w l address l data inl address r data outr clk r r/ w r [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 10 of 19 figure 9. pipelined read-to-write-to-read (oe = v il ) [20, 27, 28, 29] figure 10. pipelined read-to-write-to-read (oe controlled) [20, 27, 28, 29] notes 27. output state (high, low, or high impedance) is determined by the previous cycle control signals. 28. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 29. during ?no operation?, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrit y. switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce 0 ce 1 r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3 t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 t cklz t cd2 q n q n+4 clk ce 0 ce 1 r/w address data in data out oe [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 11 of 19 figure 11. flow throug h read-to-write-to-read (oe = v il ) [18, 20, 28, 29] figure 12. flow through read-to-write-to-read (oe controlled) [18, 20, 27, 28, 29] switching waveforms (continued) t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t sw t hw t sd t hd a n a n+1 a n+2 a n+2 a n+3 a n+4 d n+2 q n q n+1 q n+3 t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc read no operation write read clk ce 0 ce 1 address r/w data in data out q n t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t cd1 t dc t ohz read a n a n+1 a n+2 a n+3 a n+4 a n+5 d n+2 d n+3 t sw t hw t sd t hd t cd1 t cd1 t cklz t dc q n+4 t oe write read clk ce 0 ce 1 address r/w data in data out oe [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 12 of 19 figure 13. pipelined read with address counter advance [30] figure 14. flow through read with address counter advance [30] note 30. ce 0 and oe = v il ; ce 1 , r/w and cntrst = v ih . switching waveforms (continued) counter hold read with counter t sa t ha t sad t had t scn t hcn t ch2 t cl2 t cyc2 t sad t had t scn t hcn q x-1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address clk address ads data out cnten a n t ch1 t cl1 t cyc1 t sa t ha t sad t had t scn t hcn q x q n q n+1 q n+2 q n+3 a n t sad t had t scn t hcn t dc t cd1 counter hold read with counter read external address read with counter clk address ads data out cnten [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 13 of 19 figure 15. write with address counter advance (flow through or pipelined outputs) [31, 32] notes 31. ce 0 , ub , lb , and r/w = v il ; ce 1 and cntrst = v ih . 32. the ?internal address? is equal to the ?external address? when ads = v il and equals the counter output when ads = v ih . switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal cnten ads data in address t sa t ha [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 14 of 19 figure 16. counter reset (pipelined outputs) [20, 27, 33, 34] notes 33. ce 0 , ub , and lb = v il ; ce 1 = v ih . 34. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. switching waveforms (continued) t ch2 t cl2 t cyc2 clk address internal cnten ads data in address cntrst r/w data out q 0 q 1 q n d 0 a x 01a n a n+1 t sad t had t scn t hcn t srst t hrst t sd t hd t sw t hw a n a n+1 t sa t ha counter reset write address 0 read address 0 read address 1 read address n [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 15 of 19 read/write and enable operation [35, 36, 37] inputs outputs operation oe clk ce 0 ce 1 r/w i/o 0 ? i/o 17 x h x x high-z deselected [38] x x l x high-z deselected [38] x l h l d in write l l h h d out read [35] h x l h x high-z outputs disabled address counter control operation [35, 39, 40, 41] address previous address clk ads cnten cntrst i/o mode operation x x x x l d out(0) reset counter reset to address 0 a n x l x h d out(n) load address load into counter x a n h h h d out(n) hold external address blocked?counter disabled x a n h l h d out(n+1) increment counter enabled?in ternal address generation x a n h l h d out(n+1) increment counter enabled?in ternal address generation notes 35. ?x? = ?don?t care?, ?h? = v ih , ?l? = v il . 36. ads , cnten , cntrst = ?don?t care?. 37. oe is an asynchronous input signal. 38. when ce changes state in the pipelined mode, deselection and read happen in the following clock cycle. 39. ce 0 and oe = v il ; ce 1 and r/w = v ih . 40. data shown for flow through mode; pipelined mode output is delayed by one cycle. 41. counter operation is independent of ce 0 and ce 1 . [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 16 of 19 ordering information 16k x16 3.3v synchronous dual-port sram speed (ns) ordering code package diagram package type operating range 6.5 [1, 2] cy7c09269v-6ac 51-85048 100-pin thin quad flat pack commercial cy7c09269v-6axc 100-pin thin quad flat pack (pb-free) 7.5 [2] cy7c09269v-7ac 51-85048 100-pin thin quad flat pack commercial cy7c09269v-7axc 100-pin thin quad flat pack (pb-free) 9 cy7c09269v-9ac 51-85048 100-pin thin quad flat pack commercial cy7c09269v-9axc 100-pin thin quad flat pack (pb-free) cy7c09269v-9ai 51-85048 100-pin thin quad flat pack industrial 12 cy7c09269v-12ac 51-85048 100-pin thin quad flat pack commercial cy7c09269v-12axc 100-pin thin quad flat pack (pb-free) 32k x16 3.3v synchronous dual-port sram speed (ns) ordering code package diagram package type operating range 6.5 [1, 2] cy7c09279v-6ac 51-85048 100-pin thin quad flat pack commercial cy7c09279v-6axc 100-pin thin quad flat pack (pb-free) 7.5 [2] cy7c09279v-7ac 51-85048 100-pin thin quad flat pack commercial cy7c09279v-7axc 100-pin thin quad flat pack (pb-free) 9 cy7c09279v-9ac 51-85048 100-pin thin quad flat pack commercial cy7c09279v-9ai 51-85048 100-pin thin quad flat pack industrial 12 cy7c09279v-12ac 51-85048 100-pin thin quad flat pack commercial cy7c09279v-12axc 100-pin thin quad flat pack (pb-free) 64k x16 3.3v synchronous dual-port sram speed (ns) ordering code package diagram package type operating range 6.5 [1, 2] cy7c09289v-6ac 51-85048 100-pin thin quad flat pack commercial cy7c09289v-6axc 100-pin thin quad flat pack (pb-free) 7.5 [2] cy7c09289v-7ac 51-85048 100-pin thin quad flat pack commercial cy7c09289v-7axc 100-pin thin quad flat pack (pb-free) 9 cy7c09289v-9ac 51-85048 100-pin thin quad flat pack commercial cy7c09289v-9axc 100-pin thin quad flat pack (pb-free) cy7c09289v-9ai 51-85048 100-pin thin quad flat pack industrial cy7c09289v-9axi 100-pin thin quad flat pack (pb-free) 12 cy7c09289v-12ac 51-85048 100-pin thin quad flat pack commercial cy7c09289v-12axc 100-pin thin quad flat pack (pb-free) [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 17 of 19 ordering information (continued) 16k x18 3.3v synchronous dual-port sram speed (ns) ordering code package diagram package type operating range 6.5 [1, 2] cy7c09369v-6ac 51-85048 100-pin thin quad flat pack commercial cy7c09369v-6axc 100-pin thin quad flat pack (pb-free) 7.5 [2] cy7c09369v-7ac 51-85048 100-pin thin quad flat pack commercial cy7c09369v-7axc 100-pin thin quad flat pack (pb-free) cy7c09369v-7ai 51-85048 100-pin thin quad flat pack industrial 9 cy7c09369v-9ac 51-85048 100-pin thin quad flat pack commercial cy7c09369v-9axc 100-pin thin quad flat pack (pb-free) cy7c09369v-9ai 51-85048 100-pin thin quad flat pack industrial 12 cy7c09369v-12ac 51-85048 100-pin thin quad flat pack commercial cy7c09369v-12axc 100-pin thin quad flat pack (pb-free) 32k x18 3.3v synchronous dual-port sram speed (ns) ordering code package diagram package type operating range 6.5 [1, 2] cy7c09379v-6ac 51-85048 100-pin thin quad flat pack commercial cy7c09379v-6axc 100-pin thin quad flat pack (pb-free) 7.5 [2] cy7c09379v-7ac 51-85048 100-pin thin quad flat pack commercial 9 cy7c09379v-9ac 51-85048 100-pin thin quad flat pack commercial cy7c09379v-9ai 51-85048 100-pin th in quad flat pack industrial 12 cy7c09379v-12ac 51-85048 100-pin thin quad flat pack commercial cy7c09379v-12axc 100-pin thin quad flat pack (pb-free) cy7c09379v-12axct 100-pin thin quad flat pack (pb-free) 64k x18 3.3v synchronous dual-port sram speed (ns) ordering code package diagram package type operating range 6.5 [1, 2] cy7c09389v-6ac 51-85048 100-pin thin quad flat pack commercial cy7c09389v-6axc 100-pin thin quad flat pack (pb-free) 7.5 [2] cy7c09389v-7ac 51-85048 100-pin thin quad flat pack commercial cy7c09389v-7axc 100-pin thin quad flat pack (pb-free) 9 CY7C09389V-9AC 51-85048 100-pin thin quad flat pack commercial cy7c09389v-9axc 100-pin thin quad flat pack (pb-free) cy7c09389v-9ai 51-85048 100-pin thin quad flat pack industrial cy7c09389v-9axi 100-pin thin quad flat pack (pb-free) 12 cy7c09389v-12ac 51-85048 100-pin thin quad flat pack commercial cy7c09389v-12axc 100-pin thin quad flat pack (pb-free) [+] feedback [+] feedback
cy7c09269v/79v/89v cy7c09369v/79v/89v document #: 38-06056 rev. *c page 18 of 19 package diagrams figure 17. 100-pin thin plastic quad flat pack (tqfp), 51-85048 51-85048 *c [+] feedback [+] feedback
document #: 38-06056 rev. *c revised march 25, 2009 page 19 of 19 all products and company names mentioned in this docum ent may be the trademarks of their respective holders. cy7c09269v/79v/89v cy7c09369v/79v/89v ? cypress semiconductor corporation, 2001-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy7c09269v/79v/89v cy7c09369v/79v/89v 3. 3v 16k/32k/64k x 16/18 synchronous dual-port static ram document number: 38-06056 revision ecn submission date orig. of change description of change ** 110215 12/18/01 szv change from spec number: 38-00668 to 38-06056 *a 122306 12/27/02 rbi power up requirements added to maximum ratings information *b 344354 see ecn pcx added pb-free part ordering information *c 2678221 03/25/2009 vkn/aesa added cy7c09379v-12axct part. updated 51-85048 to *c. [+] feedback [+] feedback

▲Up To Search▲

Price & Availability of CY7C09389V-9AC

	To Download CY7C09389V-9AC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .